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Thread: Rebuilding my old analog console

  1. #201
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    Quote Originally Posted by Greg View Post
    This scroll fragment found in the keep of Rondor concerns the ringing of the KQO. Hmm. Now I wonder which bit is the DMux bit which enables PDM? I never noticed that until now. My Summer Madness might be missing something important. By the way it appears that no one knows what PDM stands for.

    Greg, I'm pretty sure PDM stands for Pulse-Density-Modulation which is a modulation form of an analog signal represented by a binary one. This could well makes sense in the context of the Laserium control electronics and methodologies. I'm pretty sure I'm right but it is a vague recollection in my past.

    See if this helps:

    https://en.wikipedia.org/wiki/Pulse-density_modulation
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  2. #202
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    Quote Originally Posted by Greg View Post
    This scroll fragment found in the keep of Rondor concerns the ringing of the KQO. Hmm. Now I wonder which bit is the DMux bit which enables PDM? I never noticed that until now. My Summer Madness might be missing something important. By the way it appears that no one knows what PDM stands for.
    PDM enable came from X6 pin 22 on the effect maps it's refered to as SPIRAL DIRECTION/PDM EN.
    "There are painters who transform the sun into a yellow spot, but there are others who, with the help of their art and their intelligence, transform a yellow spot into the sun." Pablo Picasso

  3. #203
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    That's possible. Even probable. Though the wiki article seems to be talking about representing an analog signal using pulses, which as I see it is unrelated.

  4. #204
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    Different wikipedia article:

    Pulse-width modulation (PWM), also known as pulse-duration modulation (PDM) or pulse-length modulation (PLM),[1] is any method of representing a signal as a rectangular wave with a varying duty cycle (and for some methods also a varying period).
    "There are painters who transform the sun into a yellow spot, but there are others who, with the help of their art and their intelligence, transform a yellow spot into the sun." Pablo Picasso

  5. #205
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    Quote Originally Posted by laserist View Post
    PDM enable came from X6 pin 22 on the effect maps it's refered to as SPIRAL DIRECTION/PDM EN.
    Jeez I should have seen that. That's awesome. Thanks!

  6. #206
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    Quote Originally Posted by laserist View Post
    Different wikipedia article:

    Pulse-width modulation (PWM), also known as pulse-duration modulation (PDM) or pulse-length modulation (PLM),[1] is any method of representing a signal as a rectangular wave with a varying duty cycle (and for some methods also a varying period).
    Thanks laserist. Your explanation makes more sense. I never new PWM was also known as PDM or PLM.
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  7. #207
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    STILL NO JOY!

    I built the circuit like Greg's and still not working. I got to be missing something basic.

    I'm confused with the FETs. On the LM schematic the gate of the FET goes to the output of the 555. On Greg's drawing the 555 signal goes to either a Source or Drain. I bought 2N3820 FETs and the Fairchild datasheet has the center pin of the FET as the gate. So I am not sure how these FET would work in Greg's layout. Greg are you using 2N3820 FETs? A basic electronics question: did I label the Drain, Gate and Source correctly on the LM schematic as seen a couple of posts ago?

    I'm also confused with the triangles on the LM schematic. Some have a +15V on themn so I assumed these needed voltage, but the only meaningful scope image I got on one axis only was a sawtooth wave and that only occured when the +15V was removed from the 2 triangles that deal with FET. I also tried to remove the +15V on the 555 triangle and the output pulsed from the 555 stopped.

    Here is a picture of the FETs - as pictured from bottom to top I think it's DGS. I also switched from using individual op amp to include using an RC4558 dual op amp as shown in the LM schematic and Greg's drawing.

    Could really use some guidance.
    Attached Thumbnails Attached Thumbnails 20240415_181547.jpg  


  8. #208
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    Quote Originally Posted by Kevint View Post
    STILL NO JOY!

    I built the circuit like Greg's and still not working. I got to be missing something basic.

    I'm confused with the FETs. On the LM schematic the gate of the FET goes to the output of the 555. On Greg's drawing the 555 signal goes to either a Source or Drain. I bought 2N3820 FETs and the Fairchild datasheet has the center pin of the FET as the gate. So I am not sure how these FET would work in Greg's layout. Greg are you using 2N3820 FETs? A basic electronics question: did I label the Drain, Gate and Source correctly on the LM schematic as seen a couple of posts ago?

    I'm also confused with the triangles on the LM schematic. Some have a +15V on them so I assumed these needed voltage, but the only meaningful scope image I got on one axis only was a sawtooth wave and that only occurred when the +15V was removed from the 2 triangles that deal with FET. I also tried to remove the +15V on the 555 triangle and the output pulsed from the 555 stopped.

    Here is a picture of the FETs - as pictured from bottom to top I think it's DGS. I also switched from using individual op amp to include using an RC4558 dual op amp as shown in the LM schematic and Greg's drawing.

    Could really use some guidance.
    It can be helpful to understand circuits like this by first breaking down the whole into its parts and analyzing what each part is contributing to the rest.
    The 555 is configured as an astable multivibrator (pulse generator) and according the the schematic its frequency is tuned to about 12.5 Hz. So its output on U1 pin 3 is pulsing between GND and close to +15v at that rate. R45 fine tunes U1's output pulse frequency. (and R42 is tied to +15v)

    It is this 0 to +15v pulse that is affecting the behavior of the two FET circuits and how their current sourcing or sinking is affecting the two A12 op amp feedback loops. The two FETs are essentially in parallel to the op amps feedback capacitors, C13 and C14. When either of the FETs are turned "ON" they create shorts across the capacitors and in the case of the first A12 controls how slowly the capacitor is discharged.

    Start with checking the output of U1, pin 3. It should be producing a pulse that goes from 0 to +15 and back to 0 at around 12.5 Hz. Is this happening? If not disconnect pin 3 so it is not connected to anything. Does the pulse happen with pin 3 free. If so, then the circuitry you are connecting U1, pin3 to is incorrectly wired.

    It looks like R54 and R57 are 33K input resistors to the inverting inputs of A12,1 and A12,2. That the feedback components are primarily capacitors makes them "integrators", or ramp generators . A11 is an op amp differential amplifier that is summing the differences between three signals, the output of A12,1 (that is reduced by the 10K pot setting that is connected between R45, 2K) and ground, along with the output of A12,2. These 3 signals provide degrees of positive and negative feedback that depend on the ratios of R20?, R51,R52 to A11's feedback resistor R49 back into the input of A12,1, producing a ramp generator or something along that line, with outputs at "N'" and "P" being the same frequency ramp signal but 90 degrees out of phase from each other.

    The other guys will be much more helpful as to how to best adjust the 10K 10-turn pot, and R53's 100K pot.

    I hope I'm close with my analysis ;-) .
    Last edited by lasermaster1977; 04-16-2024 at 16:12.
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  9. #209
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    Fascinating analysis, lasermaster1977. Give me some time and I'll 'scope out the nodes on my working circuit and see what corresponds to what you said.

    Kevin:
    The clock pulse is mostly up, and goes down for a narrow pulse to ring the circuit. You're sure your clock pulse looks good? I sort of remember not being able to definitively pin down the source gate drain thing, and eventually just trying different possibilities until it worked. One problem might be that your breadboarding skills are too advanced, and your build does not look enough like spaghetti.
    Last edited by Greg; 04-16-2024 at 16:32.

  10. #210
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    Quote Originally Posted by Greg View Post
    Fascinating analysis, lasermaster1977. Give me some time and I'll 'scope out the nodes on my working circuit and see what corresponds to what you said.

    Kevin:
    The clock pulse is mostly up, and goes down for a narrow pulse to ring the circuit. You're sure your clock pulse looks good? I sort of remember not being able to definitively pin down the source gate drain thing, and eventually just trying different possibilities until it worked. One problem might be that your breadboarding skills are too advanced, and your build does not look enough like spaghetti.
    ...does not look enough like spaghetti. Nice observation :-)

    I did some calculations on the 555 circuit. For the 555 to produce a 12.5 Hz pulse output, given C11 = 1uF, R44=1.5K, R42=47K, the R45 100K trim pot with its wiper tied to one end or the other of itself, must be adding an additional 65,200 Ohms in series with the 47K resistor. (this is a close approximation given 5 or 10% RC component tolerances.)

    The 555's positive pulse stays high .078794 seconds and is low .00104 seconds, so as Greg stated it is mostly high, with a very narrow negative going pulse.

    Therefore the 555's negative (toward 0v) going output pulse turns On the FETs for .00104 seconds and become very low resistance from Source to Drain pins. When the output pulse is positive the FETS are OFF (open circuits).

    The two integrator op amp's RC frequency response is about 482Hz but this is heavily modified by how the FETs are turning On and Off. Think of like this, when a sudden positive step input appears on the integrator's input it will charge the feedback capacitor in a linear fashion, producing a negative going voltage ramp as fast as 1/482 seconds. But the three op amps are tuned to produce two linear ramps (or is it spirals?) of the same frequency 90 degrees out of phase.
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