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Thread: The big TEC driver thread!

  1. #281
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    Quote Originally Posted by ogoun View Post
    Hi,
    A few suggestions:

    Can we also connect the overtemp line to an unused input on the v2 design? I know it is unlikely to ever be needed, but I cant think of a reason not to do it, since it should only need a pullup.
    Hi Pete, Frank and I have have already agreed to do this on V2 once we have more I/O available.
    Quote Originally Posted by ogoun View Post
    Are there any hardware issues with using this design over a wider temp range? I have a couple of ideas of where to use this, but will be needing up to +95C, down to -30C (using a +5C water cooled TEC).
    Only from the perspective of op-amp gain and firmware. We have chosen to expand the range to provide greater resolution. Simple resistor changes and firmware calibration would all that would be necessary.
    Quote Originally Posted by ogoun View Post
    Also, for a future (?V3) design, how hard would it be to drive 2 LMD18200 bridges, driving 2 TECs, but temp controlling the same thing, i.e. 2 TECs in parallel to boost the heating/cooling capacity?
    Certainly a possibility, a simple slaved bridge.
    Quote Originally Posted by ogoun View Post
    Regarding the temp monitoring signal conditioning, could we add a header that has this type of pinout:

    1. 0volts
    2. Vsupply
    3. (something like) 1-4volts temp out (from on board NTC sig conditioning)
    4. 1-4 volts temp in (to MCU, maybe via span and zero adj?)

    with a link on pins 3 and 4 for normal operation with the on-board NTC sig conditioning.

    This way, for any more esoteric analog sensor signal conditioning, a small sub board/breadboard could be made to just do the sig conditioning for whatever sensor type it is for.

    I realise that these suggestions are beyond what a diode or SS laser TEC cooler design needs to do, but if this little TEC controller works as well as I think it might, I can see it being used all over the place, as an easy, drop in module to temp control all kinds of stuff.

    Cheers,

    Pete
    It's all possible, if Frank does not feel so inclined then anyone can modify the design to suit their needs. I am releasing the source code under a GPL license, so it's free to modify etc. according to the GPL license.
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  2. #282
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    With the exception of current limiting (need to tidy up the current limiting integration) I have tonight completed V1 firmware to suit V1 hardware. I have also made some corrections to the V2 logical diagram.

    V1 Firmware
    Click image for larger version. 

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    V2 Firmware (adds serial control)
    Click image for larger version. 

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    EDIT: Frank, I have hit an issue with current limiting. As I had planned to current limit based on average TEC current - and remember the bridge current sense is peak current based on the PWM signal, I had (foolishly) planned to sample Isense at many times the PWM frequency and calculate the integral ( trapezoidal rule) of the instantaneous current samples. Alas, with this MCU I can only sample at 15K samples per second at full resolution.

    This leaves only one other software option, as per Daves suggestion to use the analog comparator that uses AIN0 and ANI1 (which you have wired approproately) however using this method I can only implement peak limiting based on the PWM signal, not the low-passed analog signal presented to the TEC following the L/C filter...

    I'll have another think about this, as I don't see how I can sucessfully determine the integral based on a comparative result... Ultimately I can see a solution uising the ANI0/ANI1 comparator that involves hardware integration of the current sense line. Perhaps R/C integration might do it. I'll await the hardware me thinks to solve this problem.
    Last edited by dnar; 02-21-2011 at 06:12. Reason: Added current limit conundrum
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  3. #283
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    Current limiting in software sounds like a bad idea to me.
    A bug in your software could lead to some fried TEC's ...

  4. #284
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    Quote Originally Posted by dnar View Post
    EDIT: Frank, I have hit an issue with current limiting. As I had planned to current limit based on average TEC current - and remember the bridge current sense is peak current based on the PWM signal, I had (foolishly) planned to sample Isense at many times the PWM frequency and calculate the integral ( trapezoidal rule) of the instantaneous current samples. Alas, with this MCU I can only sample at 15K samples per second at full resolution.

    This leaves only one other software option, as per Daves suggestion to use the analog comparator that uses AIN0 and ANI1 (which you have wired approproately) however using this method I can only implement peak limiting based on the PWM signal, not the low-passed analog signal presented to the TEC following the L/C filter...

    I'll have another think about this, as I don't see how I can sucessfully determine the integral based on a comparative result... Ultimately I can see a solution uising the ANI0/ANI1 comparator that involves hardware integration of the current sense line. Perhaps R/C integration might do it. I'll await the hardware me thinks to solve this problem.
    I don’t quite understand that one. As far as I can tell from the data sheet of the bridge, the I_sens output is an RMS value of the momentary current on the bridge, right? Aside as stated in the datasheet “It should be noted that the recirculating currents (free wheeling currents) are ignored by the current sense circuitry. Therefore, only the currents in the upper sourcing outputs are sensed.” Which I don’t think we have to worry about since we’re not driving a motor.

    I did several simulations of PWM 10-100% measuring current before and after the LC filter with the measured RMS values being equal (<1% delta) and linear to the PWM-Signal, only the peak of the AC ripple changing slightly in amplitude. So I think you can pretty much rely on the I_Sens signal within the tolerances stated. Due to the nature of the control loop I think changes in the PWM signal will be pretty subtle once stabilization has set in.

    Suggestion:

    with the current set point = 0 - 3A = 0 - 1023 ADC Increments

    After power up/reset do an Initialization/self calibration, starting a current ramp of maybe 250-1000ms on the PWM-Out from 0% to X% while reading I_Sens. When I_Sens >= current set point then stop ramp and save to limiting variable PWM-Max out.
    In normal operation cyclic confirmation of I_Sens <= current set point if not then redim. Herewith you have determined the max allowable PWM out in reference to the current set point.

    Also if changes +/- 0.25-0.5% of the current set point occur (someone is turning the trim pot) then recalibrate. Maintain output for maybe 1s so current can be measured via DMM to confirm set point and then fall back into the PID loop.

    Critical is the initial setup of the current set point, making sure to start at zero (trimmer min) before powering up!
    Last edited by Solarfire; 02-21-2011 at 23:47.

  5. #285
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    Quote Originally Posted by FourDee View Post
    Current limiting in software sounds like a bad idea to me.
    A bug in your software could lead to some fried TEC's ...
    Where I work we do current limiting/control via software for all our Cranes (Terex-Demag) without issues. Of course software bugs are a no go, but once tested and debuged I don't expect any problems down that line, unless someone screws around in the software and puts a bug in it.

  6. #286
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    Hi Frank, count on loading ATtiny84's in the prototypes. The code requires 8Kb program flash.
    avr-gcc -mmcu=attiny84 -Wall -gdwarf-2 -std=gnu99 -DF_CPU=20000000UL -Os -funsigned-char -funsigned-bitfields -fpack-struct -fshort-enums -MD -MP -MT main.o -MF dep/main.o.d -c ../main.c
    avr-gcc -mmcu=attiny84 -Wl,-Map=Solarfire-n-ice.map main.o -o Solarfire-n-ice.elf
    avr-objcopy -O ihex -R .eeprom -R .fuse -R .lock -R .signature Solarfire-n-ice.elf Solarfire-n-ice.hex
    avr-objcopy -j .eeprom --set-section-flags=.eeprom="alloc,load" --change-section-lma .eeprom=0 --no-change-warnings -O ihex Solarfire-n-ice.elf Solarfire-n-ice.eep || exit 0
    avr-objdump -h -S Solarfire-n-ice.elf > Solarfire-n-ice.lss

    AVR Memory Usage
    ----------------
    Device: attiny84

    Program: 5118 bytes (62.5% Full)
    (.text + .data + .bootloader)

    Data: 327 bytes (63.9% Full)
    (.data + .bss + .noinit)


    Build succeeded with 0 Warnings...
    I'll complete V2 soon, so we can see if it will fit, but I am thinking we may need to bump V2 to an ATmega16 or similar with 16Kb flash.
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  7. #287
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    Quote Originally Posted by dnar View Post
    Hi Frank, count on loading ATtiny84's in the prototypes. The code requires 8Kb program flash.
    I'll complete V2 soon, so we can see if it will fit, but I am thinking we may need to bump V2 to an ATmega16 or similar with 16Kb flash.
    Ok. Do you think a ATmega168 will do for V2, it has a 16k flash and is pin compatible with the momentary V2 build?

  8. #288
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    Quote Originally Posted by Solarfire View Post
    Ok. Do you think a ATmega168 will do for V2, it has a 16k flash and is pin compatible with the momentary V2 build?
    Hi mate, spot on, it has all the internal peripherals I require. Mega168 it is.

    EDIT: Sorry I didn't realize V2 was already designed around 48/88/168. You have your shit in a pile.
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  9. #289
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    Hey wayne,

    did you catch the feedback on the current limiting issue 5 posts back?

  10. #290
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    Hi mate, yeah I read them and will leave this until I get the hardware to test for sure. In the following application note, figures 5 & 10 confirm my belief that the current sensing is instantaneous and not RMS, average or otherwise.

    http://www.national.com/an/AN/AN-694.pdf

    Worst case, I will simply implement "Max PWM" limiting OR a PV attenuator after the PID loop and ignore the sense signal. I like the thought of the later as one could essentially scale the output current to suit. I would prefer closed loop control, but that's in that perfect world that only women believe exists.

    It may come down to hardware integration of the sense signal using an R/C network.

    For now, I have implemented integration of 500Hz current sampling and will take it from there once I get a hardware test platform. And there lies the problem, sampling a 100kHz PWM current signal at 500Hz is just plain wrong! Hello aliasing errors!

    I do like your idea of a POST (power on self test) current calibration run.

    BTW, I just realised we have no protection for the MCU should the sense signal exceed 5V, which it could in a TEC short circuit condition (assuming the 12v supply can deliver the current)... We should add a series resistor on the sense line and a diode to clamp the ADC input at 5V maximum (plus diode Vfwd).

    The code is complete and it compiles, so in the mean time I'll move on to V2 with serial control.

    Wayne.
    Last edited by dnar; 02-22-2011 at 04:51.
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