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Thread: Can someone explain 7 nm lithography?

  1. #1
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    Default Can someone explain 7 nm lithography?

    MY BRAIN HURTS!

    With all the recent talk about new GPUs from Nvidia and AMD, not to mention the new ZEN 3 CPU from AMD, I started thinking about these "7 nm" chip fab processes. And no matter how hard I try, I end up with the fact that someone, somewhere, must have repealed the basic laws of physics because they are so far beyond the diffraction limit (like seriously, almost 2 orders of magnitude beyond) that it's making me question our reality.

    So here's how I understand the process: UV light from an ArF eximer laser at 193 nm is passed through a metal mask to expose the photoresist that is applied to the wafer. This "develops" the photoresist layer wherever the UV light passes through the mask. Then they step the mask to the next position on the wafer and repeat the exposure process. When the whole wafer is done, then either the exposed or the unexposed portion of the photoresist is removed (depending on the type) which leaves parts of the bare wafer exposed. Then they deposit the P-type or N-type silicon as needed to create the transistor parts. Repeat for several layers to build up the parts of each transistor (not to mention all the interconnects) and you have a functional chip.

    Here's where the laws of physics break down: the diffraction limit for 193 nm light is half the wavelength, or 96.5 nm. If you try to resolve anything smaller than that, the image gets blurry. So shining the 193 nm UV light through the mask should only be able to create patterns in the photoresist that are 96.5 nm wide, and that assumes *perfect* optics.

    OK, I understand that the photoresist pattern on the chip doesn't have to be perfect, so some "blurred edges" are acceptable. Even if we assume that you can accept a 50% loss in resolution though, that still only gets you down to 48 nm. So you're still a long way away from 7 nm, and you're already at the point where the edges of your photoresist are going to look terrible, meaning that the transistor you're trying to build might end up shorting out to it's neighbor.

    So how in the name of Galileo's butthole can they manage to create structures that are only 7 nm wide when the whole process relies on the optical resolution of 193 nm UV light?

    Anyone?

    Adam

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    I randomly started reading about this a few weeks ago, because I too had similar questions about how they were getting such fine features with light presumably in the hundreds of nanometers. It turns out that it's a combination of multi-patterning, immersion lithography, and extreme UV at 13.5nm. This article is a few years old but has a really good overview of the techniques: https://semiengineering.com/why-euv-is-so-difficult/

    The gist, as I understand it, of those factors follows, but that article is really worth a read if you want to know the details.

    Multi-patterning, as I understand it, breaks a single layer down into multiple overlaid masks that each do a fraction of the required features. This has the big downside that more masks means more setup cost and more time to process each layer, especially in some techniques that require additional deposition/etch steps.

    Immersion lithography, as the name suggests, takes place with the wafer and the litho optics immersed in a fluid with a refractive index higher than that of air, which reduces the index changes that the exposure light has to pass through and thence reduces problems with diffraction.

    Supposedly, multiple exposure & immersion lithography techniques allow 7nm features to be produced with 193nm, but for typical parts requires triple or quadruple patterning, a total of 80-85 masks, and takes about 5 months to process a wafer, which is a huge economic challenge. I guess that the more masks and deposition/etch steps you have, the higher your defect rate becomes as well, so it's not a very attractive solution.

    Extreme UV, with it's much shorter wavelengths, solves a lot of those problems, but comes with its own challenges, starting with the light source. The gist of getting 13.5nm is that you produce a stream of 25micron droplets of molten tin, then you zap each droplet with a CO2 laser, twice--first to turn it into a pancake (and presumably warm it up a bit), and second to convert it to plasma, the light from which gets heavily filtered to isolate the 13.5nm. It takes about 50,000 droplets per second and a 20kW laser to produce about 250W of usable 13.5nm. Pretty wild!

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    ... IIRC, the "trick" is much simpler -- it's not "optical image projection", where the optics lawas are valid, but more "contact-masking", where even longer wavelengths can only affect the "free" areas, not the shadowed ones ...

    Viktor
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    Thanks for the info, Andrew! I agree that the article you linked to was very informative. I was not aware of this EUV process that generated 13.5 nm light by blasting droplets of molten tin with a 20 KW CO2 laser! (How cool is that?) Although it would seem that this is an uncollimated light source, right? (No resonator cavity, just a super-radiant excitation process and a bunch of mirrors to collect and focus the light...) Still, assuming they can work out the kinks, this EUV technology should allow for many more iterations of Moore's Law by permitting transistors continue to shrink in size.

    Regarding the methods currently in use with the standard ArF UV source at 193 nm though, I'm still unclear as to how multiple patterning works to get around the diffraction limit, because that limit has to apply equally to all of the masks. Are they somehow trying to "average out" the resolution errors between the different masking areas? How would that even work? Surely any errors caused by the blurry image from being below the diffraction limit would be random, no?

    As for immersion lithography, I thought that was only good for making the masks, because you can't apply any foreign liquids to the wafer (apart from the photoresist) or you risk contamination. (Plus the difference in refraction from air to water doesn't seem to be nearly enough to get down to 7 nm when the diffraction limit is 96.5 nm anyway.) Then too, I remember reading that even when they use immersion lithography to make a mask, they still have to clean up the edges with an electron beam afterwards.

    Viktor, you mentioned contact lithography... I understand how that could get around a good bit of the diffraction limit, but I understand that contact lithography usually damages the mask when it is removed, so it's only good for a few exposures. That wouldn't work for a fab that has to re-use the mask for each chip on the wafer. Unless there's a newer technology where they can remove the mask without ruining it?

    Adam

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    When I was a away from the university for a few years, I installed the high powered mode-locked laser that is used to track the droplets before the Co2 Laser strikes... On a prototype. Really fun two days. All the good stuff that positions the wafer was in another room, and I did not see that.
    I can only imagine what else is under the cover.

    Steve
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