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Thread: The big TEC driver thread!

  1. #361
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    Do you have any input protection on that driver SF? It appears you don't have even a zener diode...
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  2. #362
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    Quote Originally Posted by Solarfire View Post
    Got a little stack of the prototype LD-Driver PCBs today, will be populated shortly and I’m PICin at the code for the PIC version of the TEC-Driver.
    Looking forward to see what 250KHz pwm will do to the board size

    /Thomas

  3. #363
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    Quote Originally Posted by dave View Post
    Do you have any input protection on that driver SF? It appears you don't have even a zener diode...
    You’re right dave, no zener on the input. The input here consists of a 6:1 dividing network on a 5V RROP Amp with an amplification of 6. Making the input safe up to 30V without overdriving the amp input. The input stage has its own precision 5V supply and the output stage runs a separate RR driver for the FET @ 6-24V. I had a zener in there in the beginning until I saw that the zener was screwing up my output-linearity at higher frequencies (see graphs).
    Attached Thumbnails Attached Thumbnails No Zener.jpg  

    With Zener.jpg  


  4. #364
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    Quote Originally Posted by Badpip View Post
    Looking forward to see what 250KHz pwm will do to the board size

    /Thomas
    I’m still reading up on that part. As far as I can see at the moment, I can go with 125 kHz with an 8 bit resolution or with 250 kHz with a 7 bit resolution. There’s a shit load of clock options here that has to be sifted thru. Hell, I’m happy to have 125 kHz to work with. The option of a 7 bit resolution may also be acceptable, 250kHz is way better than 125kHz. Like I said I’m still reading up on that one. There’s some talk in the datasheet about clk frequencies up to 64MHz but I don’t know if this will have any further effect on the PWM frequency.

  5. #365
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    Quote Originally Posted by Solarfire View Post
    I’m still reading up on that part. As far as I can see at the moment, I can go with 125 kHz with an 8 bit resolution or with 250 kHz with a 7 bit resolution. There’s a shit load of clock options here that has to be sifted thru. Hell, I’m happy to have 125 kHz to work with. The option of a 7 bit resolution may also be acceptable, 250kHz is way better than 125kHz. Like I said I’m still reading up on that one. There’s some talk in the datasheet about clk frequencies up to 64MHz but I don’t know if this will have any further effect on the PWM frequency.
    14.3.8 CHANGES IN SYSTEM CLOCK
    FREQUENCY
    The PWM frequency is derived from the system clock
    frequency. Any changes in the system clock frequency
    will result in changes to the PWM frequency. See
    Section 2.0 “Oscillator Module (With Fail-Safe
    Clock Monitor)” for additional details.
    This implies 250kHz 8 bit should be possible when running the chip at 64MHz. Another nice thing is the internal 16MHz clock and 4xPLL, making it possible to run at 64MHz without any xtals taking up board real-estate. Not bad for a $2 chip

    /Thomas

  6. #366
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    Quote Originally Posted by Badpip View Post
    This implies 250kHz 8 bit should be possible when running the chip at 64MHz. Another nice thing is the internal 16MHz clock and 4xPLL, making it possible to run at 64MHz without any xtals taking up board real-estate. Not bad for a $2 chip

    /Thomas
    Yeah.. That's the part I was talkin about. I just love datasheets with 400+ pages of infos to sift thru just to get the hand full of information neccessary to get things started. I guess that means I can ditch the external xtal space which is currently reserved on the board. So... 250kHz it is.

  7. #367
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    What is happening with these drivers, find a design and get them to market!

    Thanks:
    http://www.photonlexicon.com/forums/...ted-with-parts..
    Last edited by sugeek; 07-18-2011 at 16:51. Reason: added in a link to the smd kit thread
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  8. #368
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    Quote Originally Posted by sugeek View Post
    What is happening with these drivers, find a design and get them to market!

    Thanks:
    Things are still moving along, unfortunately my co-developer dnar is not in on this so it’s from the ground up. I just had to get the LD driver off of the list of things to do first (It’s also part of the TEC/LD-driver). There is a lot of testing and tweaking involved when developing an LD-driver which will run from 6-24VDC and accept loads from 1.5-20Ohms @ up to 300kHz.

    So.. I finally settled on a MCU, PIC18F45K22 and beat my way thru the jungle of PIC I/O configuration. There is some really stupid shit involved here, had me going in circles for about 3 days just to setup the PWM frequency and duty cycle resolution. For example I need a minimum resolution of 8 bits on the PWM duty cycle, no problem, the upper (MSB) 6(8) bits are in one register and the lower (LSB) 2 bits are in the middle of another register. Now if that isn’t some stupid shit then I don’t know what is. Anyway I ended up creating a little routine to make a byte out of what should have already been one. There is not much information out there on PICs running PWM frequencies > 100kHz.

    Besides that all I/Os are now designated and configured. MCU is clocked @ 64MHz. The design was expanded to a max possible build with 2 TEC channels (for DPSS) and the temperature range is expanded to 0 – 30C°. PWM is now running @ 250kHz and the filter is re dimensioned to give a max output of 12V ± 3000mA with a max ripple of 200mV. All settings (except LD-driver) and all values (temp. current and such) will be set or monitored via RS232 on a PC.

    Possible builds:
    Single TEC-driver
    Single TEC-driver with LD-Driver
    Dual TEC-Driver
    Dual TEC-driver with LD-Driver

    Here the specs of the LD driver which will be optionally on board.

    The current values stated were derived by inducing a 0-5V 100kHz sin, sqr and saw signal with gain and bias set to give max output without clipping or distorting on the 0V or Vb Rails, then switching to 5VDC on the modulation input to read the max DC output and Power dissipation on the current 3W 0.1Rsens resistor.
    Attached Thumbnails Attached Thumbnails Load Power Table for Solarfire LD-Driver V2.02.jpg  

    Last edited by Solarfire; 07-19-2011 at 07:18.

  9. #369
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    This is starting to look veeeery interesting !

    Cheers

  10. #370
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    Quote Originally Posted by Solarfire View Post
    Dual TEC-driver
    looking forward to this!

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